Lithographic photomasks (i.e., reticles or, simply, masks) are a critical part of the integrated circuit (IC) supply chain. A chipmaker designs an IC, which is then translated into a file format. Then, a photomask is developed based on that file format. Basically, the mask is a master template for a given IC design. After a mask is developed, it is shipped to the fab. The mask is placed in a lithography scanner. The scanner projects light through the mask, which patterns the images on a wafer. Diffraction occurs when a beam of light passes through the scanner to the mask. The light waves spread out, and sometimes are accompanied by interference. Therefore, a pattern as it was designed to be printed on the wafer could become blurred or lost.
To deal with the diffraction and other issues causing the pattern printed on the wafer to become distorted, chip designers and mask makers use various resolution enhancement techniques (RETs) on the mask pattern. One RET, called optical proximity correction (OPC), is used to modify the mask patterns to improve the printability on the wafer. Among other things, OPC makes use of tiny sub-resolution assist features (SRAFs), or decoration-like shapes, on the mask. The SRAFs themselves do not print on the wafer, but instead cause the printed pattern to better match the intended pattern or target pattern. Inverse lithography technology (ILT) is a next-generation RET that enables generating an optimal mask pattern having SRAFs. Using complex mathematics, ILT improves the latitude of a process and the depth of focus for a lithography tool. In general, ILT involves receiving as an input the target patterns of an IC that are desired to be printed on the wafer. Then, models of the scanner optics and resists are formulated. Using the target patterns and the models, the optimal mask pattern, including SRAFs, is inversely calculated.
The idea of ILT was first introduced more than thirty years ago. Since then ILT has become a major area of research in the field of computational lithography. Today, ILT is mostly used in only niche applications, mainly for hot spot repair on the mask. Ultimately, however, the industry hopes to devise “full-chip ILT masks,” which involves the integration of the technology for all layers, not just for some isolated features on a particular reticle. Full-chip ILT may help ease the constraints in advanced patterning, as the technology could enable the most difficult features, such as tiny contacts, cuts and vias, in IC designs.
Unfortunately, conventional full-chip ILT is too impractical and is therefore mostly avoided. For example, generating a mask pattern for a target pattern using conventional ILT techniques can take up to ten times as long as generating a mask pattern using OPC techniques. Likewise, write times for a typical mask can be 8, 12 or 24 hours. With mask patterns generated using conventional ILT, write times are significantly longer, such as up to five days. Various methods and algorithms have been developed to attempt to address these and other problems afflicting ILT (see, e.g., B-G. Kim et. al. “Trade-off between Inverse Lithography Mask Complexity and Lithographic Performance.” Proc. SPIE vol 7379-73791M (2009); T. Cecil et. al. “Enhancing Fullchip ILT Mask Synthesis Capability for IC Manufacturability.” Proc. SPIE 7973, Optical Microlithography XXIV, 79731C (2011); Yijiang Shen, Ngai Wong, and Edmund Y. Lam, “Level-set-based inverse lithography for photomask synthesis,” Opt. Express 17, 23690-23701 (2009); and Linyong Pang, Yong Liu and Dan Abrams, “Inverse lithography technology (ILT): a natural solution for model-based SRAF at 45 nm and 32 nm,” Proc. SPIE 6607, Photomask and Next-Generation Lithography Mask Technology XIV, 660739 (May 15, 2007)), however none have been satisfactory.